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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. drv110a-q1 slvses6 ? august 2018 drv110a-q1 120- and 230-v ac, 6- to 48-v dc current controller for solenoids, relays, and valves 1 1 features 1 ? aec-q100 qualified for automotive applications: ? device temperature grade 1: ? 40 c to +125 c, t a ? internal zener diode on supply pin for high- voltage operation ? 120- and 230-v ac supply through rectifier and r s resistor ? 24-v, 48-v, and higher dc supply through r s resistor ? drives an external mosfet with pwm to control solenoid current ? external sense resistor for regulating solenoid current ? fast ramp-up of solenoid current to ensure activation ? solenoid current is reduced in hold mode for lower power and thermal dissipation ? ramp peak current, keep time at peak current, hold current, and pwm clock frequency can be set externally. they can also be operated at nominal values without external components. ? protection ? thermal shutdown ? undervoltage lockout (uvlo) ? optional status output ? 14-pin tssop package 2 applications ? electromechanical drivers: solenoids, valves, relays, contactors, switchgear, pneumatics ? ev charging station power modules, on-board chargers, battery management systems 3 description the drv110a-q1 device is a pwm current controller for solenoids. the device is designed to regulate the current with a well-controlled waveform to reduce power dissipation. the solenoid current is ramped up fast to ensure opening of the valve or relay. after initial ramping, the solenoid current is kept at a peak value to ensure correct operation, after which the current is reduced to a lower hold level to avoid thermal problems and reduce power dissipation. the peak current duration is set with an external capacitor. the peak and hold levels of the current ramp, as well as the pwm frequency, can independently be set with external resistors. external setting resistors can also be omitted if the default values for the corresponding parameters are suitable for the application. the drv110a-q1 device has an internal zener diode that limits the supply at vin to v zener for applications that require a higher supply voltage. using the internal zener, the drv110a-q1 can be powered from 120-v and 230-v ac supplies through a rectifier and current-limiting resistor. high dc voltages such as 48-v can also be accommodated this way. device information (1) part number package body size (nom) drv110a-q1 tssop (14) 5.00 mm 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. drv110a-q1 supplied by power line voltage drv110 vin 120 and 230 v ac c2 r s c1 en osc keep hold peak gnd c keep r peak r hold r osc sense out r sense m1 copyright ? 2018, texas instruments incorporated d1 l s advance information tools & software technical documents ordernow productfolder support &community
2 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 6 7 detailed description .............................................. 7 7.1 overview ................................................................... 7 7.2 functional block diagram ......................................... 7 7.3 feature description ................................................... 8 7.4 device functional modes ........................................ 12 8 application and implementation ........................ 13 8.1 application information ............................................ 13 8.2 typical application .................................................. 13 9 power supply recommendations ...................... 16 10 layout ................................................................... 16 10.1 layout guidelines ................................................. 16 10.2 layout example .................................................... 17 11 device and documentation support ................. 18 11.1 documentation support ........................................ 18 11.2 receiving notification of documentation updates 18 11.3 community resources .......................................... 18 11.4 trademarks ........................................................... 18 11.5 electrostatic discharge caution ............................ 18 11.6 glossary ................................................................ 18 12 mechanical, packaging, and orderable information ........................................................... 18 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes august 2018 * initial release. advance information
3 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions pw package 14-pin tssop top view (1) keep nc pins floating. do not connect nc pins to gnd or any other node. pin functions pin i/o description name no. en 13 i enable gnd 8 ? ground hold 4 i hold current set keep 2 i keep time set nc 1 ? no connect (1) nc 6 ? no connect (1) nc 10 ? no connect (1) nc 14 ? no connect (1) osc 5 i pwm frequency set out 11 o solenoid switch gate drive peak 3 i peak current set sense 9 i solenoid current sense status 12 o open drain status indicator vin 7 i 6-v to 15-v supply advance information 1 nc 14 nc 2 keep 13 en 3 peak 12 status 4 hold 11 out 5 osc 10 nc 6 nc 9 sense 7 vin 8 gnd
4 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. 6 specifications 6.1 absolute maximum ratings see (1) and (2) min max unit vin input voltage ? 0.3 20 v voltage on en, status, peak, hold, osc, sense, keep ? 0.3 7 v voltage on out ? 0.3 20 v t j operating junction temperature ? 40 150 c t stg storage temperature ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) hbm esd classification level 2 2000 v charged-device model (cdm), per aec q100-011 cdm esd classification level c4b all pins 500 corner pins (1, 7, 8, and 14) 750 (1) the device regulates the supply with an internal zener diode. the device sinks up to 3 ma with the added supply current. see equation 5 to find appropriate value for the r s resistor. (2) the maximum input voltage of the device depends on the clamping voltage of the internal zener diode, which changes over temperature. a current-limiting resistor is required to limit current to the zener diode if the input voltage (v in ) is greater than v zener . for more information on resistor sizing see the detailed description section and application and implementation section. (3) for v s voltages less than v zener , v in = v s . for v s voltages greater than v zener , v in = v zener . (4) 4.7- f input capacitor and full wave rectified 230-vrms ac supply results in approximately 500-mv supply ripple. 6.3 recommended operating conditions ? 40 c t a 125 c (unless otherwise noted) min nom max unit i q supply current (the device sinks additional current when v in > v zener (1) ) 1 1.5 3 ma v in voltage at the vin pin (2) (3) (see detailed description ) 6 v v s voltage directly from the supply before clamped by the zener diode 6 330 v c in input capacitor between vin and gnd (4) 1 4.7 f t a operating ambient temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report . 6.4 thermal information thermal metric (1) drv110a-q1 unit pw (tssop) 14 pins r ja junction-to-ambient thermal resistance 122.6 c/w r jc(top) junction-to-case (top) thermal resistance 51.2 c/w r jb junction-to-board thermal resistance 64.3 c/w jt junction-to-top characterization parameter 6.5 c/w jb junction-to-board characterization parameter 63.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w advance information
5 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.5 electrical characteristics v in = 14 v, ? 40 c t a 125 c, over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit supply i q standby current en = 0, v in = 14 v, bypass deactivated 200 250 a quiescent current en = 1, v in = 14 v, bypass deactivated 360 570 internally regulated supply en = 0, i vin = 2 ma, bypass activated 10.5 15 19 v en = 1, i vin = 2 ma, bypass activated 14.5 15 15.5 gate driver v drv gate drive voltage supply voltage in regulation v in v i drv_sink gate drive sink current v out = 15 v; v in = 15 v 8 15 ma i drv_source gate drive source current v out = gnd; v in = 15 v ? 15 ? 10 ma f pwm pwm clock frequency osc = gnd 15 20 27 khz d max maximum pwm duty cycle 100% d min minimum pwm duty cycle 7.5% t d start-up delay delay between en going high until gate driver starts switching, f pwm = 20 khz 50 s current controller, internal settings i peak peak current r sense = 1 , peak = gnd 270 300 330 ma i hold hold current r sense = 1 , hold = gnd 40 50 65 ma current controller, external settings t keep externally set keep time at peak current c keep = 1 f 100 ms v peak voltage of internal reference to which the sense pin voltage is compared to for i peak r peak = 50 k 900 mv r peak = 200 k 300 v hold voltage of internal reference to which the sense pin voltage is compared for i hold r hold = 50 k 150 mv r hold = 200 k 50 f pwm externally set pwm clock frequency r osc = 160 k 25 khz r osc = 200 k 20 logic input levels (en) v il input low level 1.3 v v ih input high level 1.65 v r en input pullup resistance 350 500 k input pulldown resistance 250 k logic output levels (status) v ol output low level pulldown activated, i status = 2 ma 0.3 v i il output leakage current pulldown deactivated, v(status) = 5 v 2 a undervoltage lockout v uvlo undervoltage lockout threshold 4.6 v thermal shutdown t tsu junction temperature start-up threshold 140 c t tsd junction temperature shutdown threshold 160 c advance information
6 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 typical characteristics figure 1. solenoid current, en, and pwm vs time advance information
7 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the drv110a-q1 device provides a pwm current controller for use with solenoids. the device provides a quick ramp to a high peak current value in order to ensure opening of the valve or relay. the current is held for a programmable time and then lowered to the hold current value to maintain the open state of the valve or relay while reducing the total current consumption. peak current duration, peak current amount, hold current amount, and pwm frequency can all be controlled by external components or used at default levels by omitting these components (except peak current duration). enable and disable of the switch is controlled by the en pin. the en pin contains an internal resistor network to set the pin to logic high when the en pin is floating. this feature can be used for situations where a control signal is not required and the solenoid is only energized when a supply voltage is present. such applications could be valves or contactors. the drv110a-q1 also features a wide vin range with an internal bypass regulator to maintain vin at an acceptable level. finally, the device features an open-drain pull-down path on the status pin which is enabled as long as undervoltage lockout or thermal shutdown has not triggered. 7.2 functional block diagram advance information osc vin en keep peak hold gnd sense out status r osc r s c1 v s c keep r peak r hold r sense v s l s d1 1 k 250 k 500 k ldo uvlo thermal shutdown osc pwm control sw ref 1 a + 100 mv mux v in m1
8 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 feature description the drv110a-q1 controls the current through the solenoid as shown in figure 2 . activation starts when en pin voltage is pulled high either by an external driver or internal pullup. in the beginning of activation, drv110a-q1 allows the solenoid current to ramp up to the peak value i peak and it regulates it at the peak value for the time, t keep , before reducing it to i hold . the solenoid current is regulated at the hold value as long as the en pin is kept high. the initial current ramp-up time depends on the inductance and resistance of the solenoid. once en pin is driven to gnd, drv110a-q1 allows the solenoid current to decay to zero. figure 2. typical current waveform through the solenoid 7.3.1 keep time the keep time, t keep , is set externally by connecting a capacitor to the keep pin. a constant current is sourced from the keep pin that is driven into an external capacitor resulting in a linear voltage ramp. when the keep pin voltage reaches 100 mv, the current regulation reference voltage, v ref , is switched from v peak to v hold . the internal current source is switched off, and the capacitor is grounded for discharge. the dependency of t keep from the external capacitor size can be calculated with equation 1 . (1) 7.3.2 pwm current control the current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the sense pin and controlling the external switching device gate through the out pin. during the on-cycle, the out pin voltage is driven and kept high (equal to vin voltage) allowing current to flow through the external switch as long as the voltage at the sense pin is less than v ref . as soon as the voltage at the sense pin is above v ref , the out pin voltage is immediately driven low and kept low until the next on-cycle is triggered by the internal pwm clock signal. in the beginning of each on-cycle, the out pin voltage is driven high and kept high for at least the time determined by the minimum pwm signal duty cycle, d min . because the current sense is done by comparing the voltage at the sense pin to a reference voltage, the drv110a-q1 device acts like a hysteresis controller. when the device acts like a hysteresis controller, it can make the pwm frequency and duty cycle appear uneven for some solenoids (see figure 3 ). 5 keep keep s t s c f 10 f = ? ? ? ? ? ? i peak i hold t keep t i solenoid en t advance information
9 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) (1) the drv110a-q1 device measures the voltage at the sense node (v sense ). this voltage is compared against the reference voltage (v ref ) each clock cycle. the voltage at the output node (v out ) becomes low when v sense v ref . the duty cycle (d) of the output voltage varies from 8% to 100%. in summary, the sense voltage is sampled after each rising edge of the pwm clk signal (pwm clk ) and goes low when v sense v ref at a minimum duty cycle of 8%. figure 3. drv110a-q1 current control with varying out duty cycle 7.3.3 configuring peak and hold currents i peak and i hold depend on fixed resistance values r peak and r hold as shown in figure 4 . if the peak pin or hold pin is connected to ground or r peak or r hold is less than 43.33 k (typical), then i peak is at its default value of 300 ma for i peak and 50 ma for i hold . the i peak value can alternatively be set by connecting an external resistor to ground from the peak pin. for example, if a 60-k ? (= r peak ) resistor is connected between peak and gnd, and r sense = 1 ? , then the externally set i peak level will be 900 ma. if r peak = 200 k ? and r sense = 1 ? , then the externally set i peak level will be 300 ma. ti does not recommend using a resistor from 30 k and 55 k to avoid the i peak or i hold current slipping from the maximum current setting to the default setting. in case r sense = 2 ? instead of 1 ? , then i peak = 450 ma (when r peak = 55 k ? ) and i peak = 150 ma (when r peak = 200 k ? ). the external setting of the hold current, i hold , works in the same way as the external setting for i peak but the current levels are 1/6 of the i peak levels for the same resistor setting. external settings for i peak and i hold are independent of each other. if r peak or r hold is decreased below 33.33 k ? (typical value), then the reference is clamped to the internal setting of 300 mv for peak and 50 mv for hold. use equation 2 and equation 3 to calculate the values for i peak and i hold respectively. the currents and resistor values should be chosen such that the voltage across the sense resistor is more than 30 mv. (2) ref peak peak sense peak sense v 1 900 ma 66.67 k 1 i ; 66.67 k r 2 m r r r w w = = w < < w gnd sense out r sense v s l s d1 osc pwm control v in m1 92% 10% 8% 88% 100% 70% d v sense v ref v out pwm clk pwm clk i coil v sense v ref v out advance information
10 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) (3) figure 4. i peak and i hold settings for r sense = 1 7.3.4 configuring the pwm frequency frequency of the internal pwm clock signal, pwm clk , that triggers each out pin on-cycle can be adjusted by external resistor, r osc , connected between osc and gnd. frequency as a function of resistor value is shown in figure 5 . default frequency is used when osc is connected to gnd directly. use equation 4 to calculate the pwm frequency as a function of the external fixed adjustment resistor value (greater than 160 k ? ). (4) figure 5. pwm clock frequency setting 7.3.5 voltage supply and integrated zener diode voltage at the out pin, that is the gate voltage of an external switching device, is equal to vin voltage during the on-cycle. the voltage is driven to ground during the off-cycle. vin voltages below v zener can be supplied directly from an external voltage source. supply voltages of at least 6 v are supported. the drv110a-q1 is able to regulate vin voltage from a higher external supply voltage, v s , by an internal bypass regulator that replicates the function of an ideal zener diode. this requires that the supply current is sufficiently limited by an external resistor between v s and the vin pin. an external capacitor connected to the vin pin is used to store enough energy to charge the external switch gate capacitance at the out pin. a range of current limiting resistor sizes (r s,min and r s,max ) can be calculated with equation 5 and equation 6 . this range keeps the vin current within the recommended operating conditions. r osc (k : ) f pwm (khz) 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 35 40 160 k : , 25 khz d001 (0 to 100 : , 20 khz) pwm osc osc 60 khz f 66.67 k ; 160 k r 2 m r = w w < < w advance information ref hold hold sense hold sense v 1 150 ma 66.67 k 1 i ;66.67 k r 333 k r r r : u u : u : : r hold/peak (k ) i hold/peak (ma) 0 50 100 150 200 250 0 100 200 300 400 500 600 700 800 900 1000 d001 i hold i peak
11 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) where ? i gate,ave is the current flowing to the external switch. for a mosfet, i gate,ave is equal to the external fet gate charge multiplied by f pwm . (5) (6) ideally, the drv110a-q1 device clamps the input voltage to 15 v. for configurations that do not use the en pin (force the pin high or leave it floating), the drv110a-q1 device clamps at 15 v (v zener = 15 v) across the temperature range of the device. if the en pin is set to 0, then refer to the values in table 1 to find the v zener used when calculating the value of r s , based on the temperature range of the application. because the v zener changes when the en state changes, select a value for r s that meets the current requirements at both v zener voltages. table 1. v zener value temperature range enable state v zener ? 40 c t a 125 c 1 15 v ? 40 c t a 35 c 0 15 v ? 40 c t a 45 c 0 14.2 v ? 40 c t a 55 c 0 13.9 v ? 40 c t a 65 c 0 13.5 v ? 40 c t a 75 c 0 13.1 v ? 40 c t a 85 c 0 12.7 v ? 40 c t a 95 c 0 12.3 v ? 40 c t a 105 c 0 12 v ? 40 c t a 115 c 0 11.4 v ? 40 c t a 125 c 0 11 v the open-drain pulldown path at the status pin is deactivated if the undervoltage lockout or thermal shutdown blocks have triggered or if the en pin is low. advance information s,mindc zener s,max gate,ave v v r 1 ma i s,max dc zener s,min gate,ave v v r 3 ma i
12 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 device functional modes 7.4.1 normal mode the drv110a-q1 transitions through three different states in normal mode: off state in the off state, the en pin is low and the pwm output is off. peak state the peak state begins when the en pin is set high, and ends when the t keep time has been reached. during this state, the pwm operates to reach the i peak current set by the r peak resistor. hold state in the hold state, the t keep time has been reached, and the pwm continues to operate but at the i hold level. this continues until the en pin is set low again and the pwm turns off. 7.4.2 shutdown the drv110a-q1 turns off the gate driver in undervoltage lockout (vin < 4.6 v) or thermal shutdown (t j > 160 c). if temperature shutdown is activated, the drv110a-q1 resumes operation when the junction temperature is below 140 c. the shutdown conditions are expressed by the status pin going to the high- impedance state. a pullup resistor can be connected to the status pin so these conditions may be observed by a microcontroller. table 2 provides an explanation of this operation. table 2. shutdown operation conditions output pins en uvlo tsd status out 0 x x hi-z low 1 0 0 pulled down high or pwm 1 x 1 hi-z low 1 1 x hi-z low advance information
13 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the drv110a-q1 device is designed to operate a solenoid valve or relay. for detailed information on using the drv110a-q1 with 230 v ac solenoids. a typical dc input design will be outlined in typical application . approximate resistor and capacitor values for the peak current, hold current, sense, and keep time will be derived for a sample application. 8.2 typical application figure 6. drv110a-q1 powered by a rectified ac power source advance information drv110 vin 120 and 230 v ac c2 r s c1 en osc keep hold peak gnd c keep r peak r hold r osc sense out r sense d1 l s m1 copyright ? 2016, texas instruments incorporated
14 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) figure 7. drv110a-q1 powered by a dc power source greater than 15 v 8.2.1 design requirements the key elements to identify here are the system input voltage, peak current, hold current, and peak keep time values required for the solenoid or relay being used. with these values, approximate r s , r peak , r hold , c keep , and r sense values can be determined and the proper fet and diode can be identified. r osc can be varied in order to tune the circuit to the chosen solenoid or relay. 8.2.2 detailed design procedure 8.2.2.1 current limiting resistor selection the temperature range, input voltage, and enable state must be considered when selecting the current limiting resistor. these values must be considered because the zener clamping voltage of the drv110a-q1 device starts dropping from its ideal 15 v at temperatures greater than 45 c when the en pin is pulled low. applications that leave the en pin floating or pulled high at all times only require a current-limiting resistor when the input voltage is greater than 15 v across all temperature. while using a current-limiting resistor is not required when the supply voltage (v s ) is less than the zener clamping voltage, v zener , ti recommends populating a small resistor in case of possible input voltage transients during operation. at the very least, ti recommends placing a resistor footprint jumped by a 0- ? resistor. table 3 lists recommended resistor values for voltages close to v zener and common voltages greater than v zener for different enable states. drv110 vin r s c1 en osc keep hold peak gnd c keep r peak r hold r osc sense out r sense d1 l s m1 copyright ? 2016, texas instruments incorporated 16 v to 48 v advance information
15 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table 3. recommended resistor values ? 40 c t a 125 c supply voltage recommended current- limiting resistor en pulled high or floating < 15 v 500 24 v 9 k 48 v 33 k 110 v to 120 v 100 k 220 v to 240 v 200 k en toggled between 0 and 1 10 v 510 11 v 510 12 v 1 k 13 v 2 k 14 v 3 k 15 v 3.9 k 24 v 13 k 48 v 36 k 110 v to 120 v 100 k 220 v to 240 v 200 k 8.2.2.2 passive component selection with the selected peak current, hold current, and peak keep time values, the values of r peak , r hold , c keep , and r sense can be determined. table 4 lists the example values and results from calculation. table 4. example application values when r sense = 1 ? variable value device values calculated from peak current 150 ma r peak = 400 k equation 2 hold current 50 ma r hold = 200 k or connect hold to ground equation 3 keep time 100 ms c keep = 1 f equation 1 pwm frequency 20 khz r osc = shorted to ground equation 4 use equation 2 and equation 3 to calculate the values of the r peak resistor and r hold (if applicable) resistor. for the sample values, the r peak resistor is set to 400 k and the r hold resistor is shorted to gnd. ti recommends using a 0- resistor for prototyping in case changes to this value are desired. next, select the value of the c keep capacitor based on equation 1 . for the sample value, the c keep capacitor is set to 1 f. the r osc resistor is initially be shorted to gnd, but a 0- resistor is also recommended for prototyping. additionally, a low-pass filter on the sense line can be added in a high-noise environment and is recommended for prototyping. the typical value for the low pass filter resistor is 1 k and the typical value for the filter capacitor is 100 pf. the value of sense resistor can be selected based on the preference of the designer. the only restriction is that the voltage across the sense resistor (found by the r sense resistance times the i hold current) must be greater than 30 mv for reliable operation. the external fet and current recirculation diode must be selected based on the current values defined in and the supply voltage. the current recirculation diode should be a fast recovery diode. advance information
16 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.3 application curve r osc = 0 r peak = 400 k r hold = 0 r sense = 1 c keep = 1 f l ind = 1 h r ind = 50 measured on the evm figure 8. i solenoid , en, and v in vs time 9 power supply recommendations the input supply range must be at least 6 v, and needs a current-limiting resistor above v zener . an input capacitor of 4.7 f (typical) is required as well. i q max is 3 ma, but additional current will be required to operate the solenoid or relay. 10 layout 10.1 layout guidelines routing for the sense pin should be careful to avoid noise sources. routing for the output node and sense node should be minimized. the trace for the solenoid or relay current should be wide in order to prevent any unexpected voltage drop. make sure that no connect (nc) pins are kept floating and are not connected to gnd or any other node. advance information
17 drv110a-q1 www.ti.com slvses6 ? august 2018 product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.2 layout example the tida-00284 ti design is shown as an example of good layout practices with the drv110a-q1. the tida-00284 design is not intended for automotive applications. figure 9. layout schematic advance information
18 drv110a-q1 slvses6 ? august 2018 www.ti.com product folder links: drv110a-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation, see the following: ? texas instruments, drv110 and drv120 evaluation modules (evm) user ' s guide 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 27-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples PDRV110AQPWRQ1 active tssop pw 14 2000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

important notice texas instruments incorporated (ti) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. ti ? s published terms of sale for semiconductor products ( http://www.ti.com/sc/docs/stdterms.htm ) apply to the sale of packaged integrated circuit products that ti has qualified and released to market. additional terms may apply to the use or sale of other types of ti products and services. reproduction of significant portions of ti information in ti data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such reproduced documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyers and others who are developing systems that incorporate ti products (collectively, ? designers ? ) understand and agree that designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that designers have full and exclusive responsibility to assure the safety of designers ' applications and compliance of their applications (and of all ti products used in or for designers ? applications) with all applicable regulations, laws and other applicable requirements. designer represents that, with respect to their applications, designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. designer agrees that prior to using or distributing any applications that include ti products, designer will thoroughly test such applications and the functionality of such ti products as used in such applications. ti ? s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, ? ti resources ? ) are intended to assist designers who are developing applications that incorporate ti products; by downloading, accessing or using ti resources in any way, designer (individually or, if designer is acting on behalf of a company, designer ? s company) agrees to use any particular ti resource solely for this purpose and subject to the terms of this notice. ti ? s provision of ti resources does not expand or otherwise alter ti ? s applicable published warranties or warranty disclaimers for ti products, and no additional obligations or liabilities arise from ti providing such ti resources. ti reserves the right to make corrections, enhancements, improvements and other changes to its ti resources. ti has not conducted any testing other than that specifically described in the published documentation for a particular ti resource. designer is authorized to use, copy and modify any individual ti resource only in connection with the development of applications that include the ti product(s) identified in such ti resource. no other license, express or implied, by estoppel or otherwise to any other ti intellectual property right, and no license to any technology or intellectual property right of ti or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti products or services are used. information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. use of ti resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. ti resources are provided ? as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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